The data storage component of an STT-MRAM (Spin Torque Transfer Magnetic Random Access memory) is a magnetic tunnel junction (MTJ) cell. The write operation uses electrical current to switch the magnetization direction of the free layer (storage layer) relative to that of the reference layer of the MTJ.
A typical type of magnetoresistive random access memory (MRAM) cell including a magnetic tunnel junctions (MTJ) will be described as examples of devices that can be used with the method of the invention. An MTJ can be designed for in-plane or perpendicular magnetization of the MTJ layer structure with respect to the film surface. The MTJ includes a free magnetic layer, a nonmagnetic spacer or junction layer, and a reference magnetic layer. Additional layers can be included such as an antiferromagnetic exchange coupling layer, a pinned magnetic layer and an antiferromagnetic layer. An MRAM cell structure typically includes a top metal contact and a bottom metal contact. The metal contacts are also referred to as electrodes. The reference magnetic layer has a fixed magnetization direction. The free magnetic layer has a magnetization direction that is switchable in either of two directions. The resistivity of the whole MTJ layer stack changes when the magnetization of the free layer changes direction relative to that of the reference layer, exhibiting a low resistance state when the magnetization orientations of the two ferromagnetic layers are substantially parallel and a high resistance when they are anti-parallel. Therefore, the cells have two stable states that allow the cells to serve as non-volatile memory elements.
The MRAM cells in an array on a chip are connected by metal word and bit lines. Each memory cell is connected to a word line and a bit line. The word lines connect rows of cells, and bit lines connect columns of cells. Typically CMOS control structures include a selection transistor which is electrically connected to the MTJ stack through the top or bottom metal contacts. The direction of the current flow is between top and bottom metal contacts.
Reading the state of the cell is achieved by detecting whether the electrical resistance of the cell is in the high or low state. Writing the cells requires a sufficiently high DC current flowing through the MTJ stack between the top and bottom metal contacts to induce a spin transfer torque that orients (switches) the free layer into the desired direction. The amount of current needed to write the cell is at least slightly higher than the current that flows during the read process, so that a read operation does not change the state of the cell.
The bit-error rate (BER) is defined, herein as the number of un-switched events divided by the total number of switching attempts, under the same writing condition, on a given MTJ cell. For commercial application of STT-MRAM, the data writing, i.e. free layer switching process by a write current, must have a very low bit-error rate. For example, it has been suggested that commercialization of STT-MRAM with 64 Mb density, requires a 10−9 BER for both read and write operations. Detection of such very low BER values requires a comparably large number of switching attempts and reading operations which can require elapsed times that are impractical and/or too costly using the prior art. For example, traditional BER measurement of MTJ cells at the wafer level uses a pulsed write operation, followed by a slow speed read (resistance sensing), and then a reset by a field or a reverse pulse. This entire process is too slow (<103 attempts per second) to enable large (≧107) amount of switching events on large number of devices for statistical significance.
Using the prior art testing method, to produce more than 100 k (105) switching attempts per second and record the switching result after each attempt, each MTJ cell will need to be embedded in a STT-MRAM CMOS circuitry, and also packaged, to enable STT-MRAM memory test utilizing the logic of the CMOS circuit.
Therefore, there is a need for a way to test the BER of MTJ cells with a rate of more than 105 switching per second at the wafer level. Such a method can provide a valuable advantage in predicting MTJ cell BER performance in real world applications at early MRAM development stages and, therefore, reduce cost significantly. Additionally, by correlating BER performance across wafers with known MTJ properties can also provide insight of physical causes of bit-errors and reduce STT-MRAM development time to reach the target BER specification.